This invention relates to binary multiplication. More specifically, the invention is concerned with data processing apparatus having a binary multiplication capability.
U.S. patent specification No. 4,228,518 describes a data processing apparatus having an arithmetic and logic unit (ALU) and an operand register (A) connected to one input of the ALU. The ALU is capable of performing various elementary operations such as addition or subtraction. Multiplication and division can also be performed, using a special shift register (M). For multiplication, one of the operands (the multiplier) is initially loaded into the M-register, and the A-register is set to zero. Each bit of the multiplier is then shifted out in turn, starting from the least significant bit. If the multiplier bit is 1, the other operand (the multiplicand) is added to the contents of A-register; otherwise, zero is added. In either case, the result of the addition is shifted one place to the right and then loaded back into the A-register, the least significant bit being inserted into the most significant end of the M-register. This is repeated until all the bits of the multiplier hve been used. At the end of the multiplication, the A-register holds the most significant bits of the product, and the M-register holds the least significant bits.
It can be seen that the arrangement described above the M-register represents an additional item of hardware which is provided specially for use in multiplication (and division).
The object of the present invention is to provide a means for performing multiplication without the need for an additional register.